Hardware Reference

Pinout & GPIO

Pin-by-pin map of how the Sixfab Edge AI Expansion Board for Raspberry Pi 5 connects to its host. Power flows up to the Raspberry Pi 5 through pogo pins on the GPIO header underside; data flows through the 40 mm PCIe FFC and a USB Bridge PCBA. Every one of the 40 GPIO pins passes through unused, so the entire header stays free for a top-mounted HAT or your application.

Raspberry Pi 5 Pogo-pin power 40 mm PCIe FFC 3× M.2 slots 0 GPIO pins consumed

Edge AI Expansion Board · Hardware Reference · Pinout & GPIO · Updated 2026-05-14

Which Pi 5 pins does the Edge AI Expansion Board use?

The Sixfab Edge AI Expansion Board for Raspberry Pi 5 mounts under the Pi 5 and contacts four pogo points on the underside of the GPIO header: two 5 V pins and two GND pins. No GPIO data pins are consumed. Every one of the 40 pins on the GPIO header passes through unused, including the HAT+ EEPROM bus on BCM 0 / BCM 1, so any standard top-mounted HAT can sit on the Pi 5 at the same time. The high-speed link to the DEEPX NPU runs over a separate 40 mm PCIe FFC, and the NVMe SSD and LTE/5G modem reach the Pi 5 through a dedicated USB Bridge PCBA. Neither pathway touches the GPIO header.

Pogo-pin power map

The Expansion Board back-powers the Raspberry Pi 5 through four spring-loaded pogo pins that touch the underside of the Pi 5's 40-pin GPIO header. There is no data on these contacts: only the 5 V rail and ground return.

5 V power · 2 pogo points GND return · 2 pogo points

Pi 5 header pin (underside)

Rail

Function

Pin 2

5 V

Primary 5 V back-power into the Pi 5 from the Expansion Board's USB-C PD input.

Pin 4

5 V

Second 5 V pogo point. Doubled rail capacity keeps current per contact within the 3 A header rating.

Pin 6

GND

Ground return.

Pin 9

GND

Ground return.

Electrical headroom on the pogo path

5 V rail · per pogo

3 A per pin

Standard 2.54 mm header pin rating. With two 5 V pogo points in parallel, the total 5 V capacity into the Pi 5 is 6 A.

Ground return

2× GND

Doubled to match the 5 V doubled rail. Carries the full return current of the powered stack.

Source · USB-C PD

27 W min 45 W recommended

Negotiated PD profiles: 5 V/5 A, 9 V/3 A, or 12 V/2.25 A at 27 W. PSUs below 27 W cause under-voltage warnings.

Power input rule

Single source

Power the stack through the Expansion Board's USB-C port only. A protective plug for the Pi 5's own USB-C port ships with the kit to prevent back-feeding.

Pogo-pin power delivery is reliable only when the 5 mm M2.5 male-female spacers between the Expansion Board and the Pi 5 are securely tightened. Loose spacers cause intermittent contact, brown-outs, and SSD disconnects. Finger-tight is enough; do not over-torque.

High-vibration deployments (drones, mobile robots) have not yet been validated. Long-term reliability of the pogo connection under sustained vibration is unverified.

40-pin GPIO header pass-through

The Expansion Board does not consume any GPIO pins for communication. The 5 V and GND pogo points sit under the header for power, but every signal pin (every GPIO, SPI, I²C, UART, PWM, and even the HAT+ EEPROM bus on BCM 0 / BCM 1) remains fully available to your application or a stacked HAT.

5 V power · pogo backfed GND · pogo backfed Free · pass-through to user

Figure 1. Raspberry Pi 5 40-pin GPIO header, Edge AI Expansion Board view. The four pogo-pin power contacts on the Pi 5 underside are highlighted (5 V on pins 2 and 4; GND pogo points sit on two of the eight GND positions on the header). Every signal pin remains free.

Zero-GPIO footprint

0 of 40 signal pins consumed for communication · 4 pogo points for power backfeed only

5 V pogo

Pins 2, 4 · backfeed

GND pogo

2 GND pins · typical

Free signals

GPIO · SPI · I²C · UART · PWM · HAT+ EEPROM

Unlike a HAT, the Expansion Board mounts under the Raspberry Pi 5 and does not present a HAT+ EEPROM. BCM 0 / BCM 1 (pins 27 and 28) are free, so a top-mounted HAT+ board can use the ID bus normally; its EEPROM will be the only one on the bus.

PCIe FFC connector

The Expansion Board reaches the Raspberry Pi 5's PCIe interface through a dedicated 40 mm × 8.5 mm FFC (Flexible Flat Cable), separate from the GPIO header. This cable carries the high-speed PCIe Gen 2 (default) or PCIe Gen 3 link to the DEEPX DX-M1 NPU installed in the M.2-PCIE slot.

Cable specification

Property

Value

Cable size

40 mm × 8.5 mm. Sixfab-manufactured FFC, included in the box.

Pi 5 end label

"RPI5". Connects to the Raspberry Pi 5's PCIe FFC port.

Expansion Board end label

"EDGE_AI". Connects to the Expansion Board's PCIe FFC connector.

Pin 1 marking

Arrow symbol and the number "1" on each end. Align with the matching markings on both PCB connectors.

Contacts orientation

When seated, the printed labels face OUT (visible to you); the metal contact pins face IN toward the PCB.

Substitution

Using a longer or different cable is not recommended. PCIe signal integrity is validated only for the supplied 40 mm cable.

Electrical envelope

Link width & generation

PCIe Gen 2 x1 · default

Gen 3 x1 is supported but disabled by default on Raspberry Pi 5. Enable with dtparam=pciex1_gen=3 in /boot/firmware/config.txt.

Measured throughput

~400–450 MB/s

At PCIe Gen 2. Rises to ~800–900 MB/s at PCIe Gen 3. NPU has exclusive access to the lane; NVMe and cellular take the USB path, not the PCIe path.

Boot-time discovery

Automatic

On a recent Raspberry Pi OS, the PCIe interface initializes automatically. The DEEPX device appears in lspci from first boot; no bootloader configuration is required for discovery.

Signal groups on the FFC

The 40 mm FFC follows the standard Raspberry Pi 5 PCIe FFC convention. The cable carries the PCIe Gen 2 / Gen 3 x1 differential pairs, the 100 MHz reference clock, the PCIe sideband control signals, and interleaved ground returns. The high-level signal groups are summarized below.

Signal group

Description

TX± / RX±

PCIe x1 differential transmit and receive pairs. High-Speed Differential Signaling carries the data between the Pi 5 SoC (BCM2712) and the DEEPX DX-M1.

REFCLK±

100 MHz PCIe reference clock differential pair.

PERST# / WAKE# / CLKREQ#

PCIe sideband control: reset, wake, and reference-clock request. Driven by the Pi 5.

GND

Return paths interleaved between high-speed pairs for impedance control.

The 40 mm FFC has two clearly labeled ends. Connect the end marked RPI5 to the Raspberry Pi 5's PCIe FFC port, and the end marked EDGE_AI to the Expansion Board's connector. Inserting the cable backwards prevents NPU detection on lspci. If the NPU is missing from lspci after a fresh build, the labels facing OUT and contacts facing IN is the first thing to re-verify.

Always power off the Pi 5 and disconnect the USB-C cable before connecting or disconnecting the FFC. The Edge AI Expansion Board does not support hot-plug. The full mount, cable, and power-on sequence is documented in the Quickstart.

USB Bridge PCBA

Storage and cellular do not reach the Raspberry Pi 5 through the PCIe FFC, and they do not use the GPIO header either. Instead, an internal USB 3.2 Gen 1 hub on the Expansion Board connects to one of the Pi 5's blue USB 3.0 ports through a short USB Bridge PCBA. The NVMe SSD and the LTE/5G modem are children of this hub.

Property

Value

Standard

USB 3.2 Gen 1 (5 Gbps). Equivalent to USB 3.0 / USB 3.1 Gen 1.

Connection to Pi 5

Via the USB Bridge PCBA into one of the two blue USB 3.0 ports on the Raspberry Pi 5. Not through pogo pins; not through the PCIe FFC.

Children on the hub

NVMe SSD (via on-board Realtek RTL9210B-CG USB-to-NVMe bridge); LTE/5G modem (M.2 Key-B, USB enumeration).

Pi 5 ports available after bridge

1× USB 3.0 + 2× USB 2.0 remain free for peripherals (keyboard, mouse, camera).

Shared bandwidth ceiling

All Pi 5 USB ports share the RP1 chip's 5 Gbps aggregate bandwidth. Total current across all USB ports is limited to 1.6 A; avoid adding more high-draw USB devices on top of the modem and SSD.

Verifying the bridge after assembly

After the Pi 5 boots, the internal hub and its devices appear in lsusb. The Realtek bridge (NVMe) and the cellular modem each enumerate under the hub:

Expected output lsusb

Example modem: Quectel RM520N-GL

$lsusb Bus 002 Device 003: ID 2c7c:0125 Quectel Wireless Solutions Co., Ltd. RM520N-GL Bus 002 Device 002: ID 0bda:9210 Realtek Semiconductor Corp. RTL9210 NVMe Bridge Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub

Bus 002 Device 003 is the LTE/5G modem. The VID:PID depends on which M.2 Key-B module is installed; 2c7c:0125 corresponds to the Quectel RM520N-GL.
Bus 002 Device 002 is the Realtek RTL9210 USB-to-NVMe bridge. This VID:PID (0bda:9210) is fixed for any NVMe in the M.2-SSD slot.
Bus 002 Device 001 is the internal USB 3.0 root hub that hosts the bridge and the modem.

M.2 slots

The Expansion Board carries three M.2 slots. Each is labeled on the silkscreen and routed to a different data path: PCIe for the AI accelerator, USB for storage and cellular.

M.2-PCIE

Key M

Direct PCIe Gen 2 / Gen 3 x1 via the 40 mm FFC. Intended for the DEEPX DX-M1 NPU; other M.2 PCIe devices (e.g. Raspberry Pi NVMe, Hailo) work but are unsupported.

2230 2242 2260 2280

M.2-SSD

Key M

USB 3.0 via the on-board Realtek RTL9210B-CG USB-to-NVMe bridge. NVMe SSDs only; M.2 SATA is not supported. Validated up to 2 TB.

2230 2242 2260 2280

CELLULAR LTE/5G

Key B

USB 3.2 Gen 1 via the internal hub. Pairs with one nano-SIM slot; eUICC nano SIMs supported, no on-board eSIM chip.

M.2 cellular module

Mounting hardware per slot

Securing screw

M2 × 6 mm

Flat-head. One per module. Finger-tight only; do not over-torque into the PCB stand-off.

3D-printed spacer

DX-M1 slot

A small 3D-printed spacer ships in the kit and sits between the DX-M1 module and the mounting hole in the M.2-PCIE slot. Place it before tightening the M2 screw.

Insertion angle

30°

Insert each M.2 module at a 30° angle, seat the gold contacts fully, then press flat and secure with the M2 screw.

Power-gating behaviour

No PCIe = no NPU

The DX-M1 module stays inactive until the PCIe FFC is connected. Modules in the USB-routed slots do not function unless the USB Bridge PCBA is also seated.

Fan connector, test points, jumpers

A few practical reference facts about what is, and what is intentionally not, populated on the Expansion Board.

Fan connector

There is no dedicated fan connector on the Expansion Board itself. The Expansion Board is designed to work alongside the Raspberry Pi 5's own cooling infrastructure: the official Raspberry Pi 5 Active Cooler plugs into the Pi 5's 4-pin JST-SH fan header, which sits on top of the Pi 5 and is unaffected by anything happening below. PWM speed control through the Pi 5 header works exactly as it does on a bare Pi 5.

The Expansion Board mounts under the Pi 5 and is fully compatible with the Active Cooler installed on top.

Test points and debug pads

None. The Expansion Board does not expose hardware test points or debug pads. Diagnostics are software-side: lspci for the NPU, lsusb for the SSD and modem, dxrt-cli -s and dxtop for the runtime, dmesg | grep -i dx for boot-time kernel evidence.

Solder jumpers

None. There are no solder jumpers (SJ) or user-configurable hardware bridges on the Expansion Board. All configuration happens in software (config.txt, raspi-config, the sixfab-dx package).

Power-on button and watchdog

The Expansion Board has no power-on button of its own. To safely shut down the stack, use the Raspberry Pi 5's own button, or sudo shutdown -h now from the OS. There is no Expansion-Board-side watchdog: the hardware watchdog you can use is the one already on the Raspberry Pi 5.

HAT stacking

Because the Expansion Board consumes zero GPIO pins and mounts under the Raspberry Pi 5, the Pi 5's 40-pin header stays fully available on top. A standard HAT can sit on the Pi 5 at the same time as the Expansion Board sits under it.

Other HAT (optional, on top)

Any standard Pi 5 HAT. Consult Sixfab before adding a HAT that needs external power.

Optional

Raspberry Pi 5

Host platform. The GPIO header is on top; the four pogo points sit under the header on the Pi 5 underside.

Host

Sixfab Edge AI Expansion Board

Under the Pi 5. Carries the DX-M1 NPU, the NVMe slot, and the LTE/5G slot. Consumes zero GPIO pins.

This board

Work surface

15 mm F-F stand-offs lift the Expansion Board off the bench. The full stack height is ~36.26 mm.

Base

Stacking compatibility

HAT or accessory

Compatible

Notes

Standard Raspberry Pi 5 HATs

Yes

The Expansion Board uses no GPIO pins for communication, so any HAT designed for Pi 4 or Pi 5 that draws its power from the header and communicates over the header is fully supported.

Raspberry Pi 5 Active Cooler

Yes

Plugs into the Pi 5's own 4-pin JST-SH fan header on top. PWM control works as on a bare Pi 5.

HATs requiring external power

Check first

If the HAT has its own DC input, contact Sixfab before deploying. The combined power budget on the Pi 5 5 V rail needs review.

Sixfab Base HAT (alongside Cellular)

Redundant

Not incompatible, but the Expansion Board already carries an M.2 cellular slot, so a Sixfab Base HAT for cellular on top would duplicate that subsystem.

Off-the-shelf Pi 5 case

Generally no

Stack height (~36.26 mm) and the under-board footprint make most standard Pi 5 enclosures incompatible.

Second Expansion Board (stacked)

Not supported

Only one Expansion Board per Raspberry Pi 5. Multiple units in a deployment is fine, one per host.

Board layout

Top-side and bottom-side images of the Expansion Board PCB are distributed as a draftsman file packaged with the product (per Q&A Q47). The file marks all major connectors, the 3× M.2 slots, the nano-SIM tray, the USB-C PD input, the PCIe FFC connector, the four LEDs, the four pogo-pin contacts, and the mounting holes (4× M2.5 + 3× M3). Key dimensional facts are summarized below.

Key dimensional facts

Property

Value

Base PCB

87 × 88 mm

Footprint with connectors

88.46 × 89.19 mm. Including USB-A protrusion (X-axis) and USB-C protrusion (Y-axis).

Mounting holes

4× M2.5 (top-side, Pi 5 stack) + 3× M3 (for system integration).

Stand-off kit

4× M2.5 F-F 15 mm (base) + 4× M2.5 M-F 5 mm (between Expansion Board and Pi 5). Included.

Total Z-stack with Pi 5

~36.26 mm. From the bottom of the 15 mm stand-offs to the tallest component on the Pi 5 (the dual USB 3.0 connector).