Quickstart
From unboxed kit to first inference on the Sixfab Edge AI Expansion Board
Assemble the under-board stack, enable PCIe Gen 3 in config.txt,
install the DEEPX runtime, and verify all three subsystems (NPU, NVMe, cellular)
in one pass. End to end, around 30 minutes once the M.2 modules are on hand.
Intelligented by DEEPX. Built on Raspberry Pi.
Six steps, around 30 minutes.
Power off your Raspberry Pi 5, install the M.2 modules you need
(NVMe SSD, DEEPX DX-M1, LTE/5G modem) and assemble the under-board stack with the
40 mm PCIe FFC cable, add three lines to /boot/firmware/config.txt to
enable PCIe Gen 3 and full USB current, install the DEEPX runtime with
sudo apt install sixfab-dx, verify the NPU with dxrt-cli -s
(plus lsblk and ping -I usb0 for the storage and cellular
subsystems), then run run_hello_world for live YOLOv8 detection on the NPU.
Before you start
This Quickstart is one of three paths through the Edge AI Expansion Board documentation. Pick the one that matches what you want to build. You can always come back here when you need the runtime up and running.
The procedure
Six steps. The first five set up the hardware, OS, and software stack; the sixth runs your first inference. Each step's commands are self-contained, so copy them in order.
Check the prerequisites and supported host platform
The Edge AI Expansion Board is an under-board baseboard for Raspberry Pi 5. Confirm the host platform and the M.2 modules you need are on hand before you open the antistatic bag.
What you need
M.2-PCIE slot, so no separate purchase is needed to begin AI inference.
run_hello_world detection demo. The demo also runs against a stored video file if no camera is connected.
Supported host platforms
- Raspberry Pi 5, the only supported host platform.
- All current Raspberry Pi 5 revisions: 2 GB, 4 GB, 8 GB, 16 GB.
- Raspberry Pi 4 and earlier.
- Compute Module 4 / Compute Module 5 (including CM5 IO Board).
- Non-Raspberry Pi SBCs (Orange Pi, Rock Pi, Jetson, etc.).
What's in the box
The kit ships ready to assemble. The DEEPX DX-M1 module is the AI engine of the stack and arrives pre-flashed with current runtime firmware; all spacers, screws, the PCIe FFC cable, and the passive cooler ship in the same box.
M.2-PCIE slot, pre-flashed with current runtime firmware. The AI accelerator the rest of this guide brings up.
Raspberry Pi 5, the other labelled Edge AI.
Assemble the under-board stack
The Expansion Board sits underneath the Raspberry Pi 5. Three M.2 modules slot into the board first, then the board stacks onto the Raspberry Pi 5 via M2.5 spacers, and the 40 mm PCIe FFC cable connects the two PCBs. Pogo pins on the Expansion Board top side back-power the Raspberry Pi 5 through the GPIO header's 5V and GND pins.
The Expansion Board is not hot-pluggable. Disconnect the USB-C power supply completely before installing or removing the Expansion Board or any M.2 module. Mounting under power can damage the PCIe FFC connector, the DEEPX silicon, or the Raspberry Pi 5.
Touch a grounded metal object or wear an ESD wrist strap before handling the PCBs. Handle every board by its edges. Assemble on a non-conductive surface like an antistatic mat or a wooden desk, never on carpet or plastic.
Three M.2 slots, three jobs
Each slot is labelled on the silkscreen. The AI accelerator goes in
M.2-PCIE only; the other two slots host storage and cellular over the
internal USB hub.
/dev/sda. Use one of the included
M2 module plastic spacers between the SSD and the board.
Assembly order
- Install the spacers. Screw the 4× M2.5 male-female 5 mm spacers into the top side of the Expansion Board (the side with the M.2 slots), one in each corner mounting hole. Screw the 6× M2.5 female-female 15 mm spacers into the bottom side as the base standoffs: four at the corners and two along the long edges, matching the hole pattern.
- Install the M.2 modules. The DEEPX DX-M1 ships
pre-installed in the
M.2-PCIEslot, so you can skip it. For each additional module you are using: insert at 30° into its labelled slot, fully seat the gold contacts, drop a 3D-printed M2 module spacer between the far end of the module and the board, press the module flat, then secure it with an M2 × 6 mm flat-head screw. Repeat for the NVMe SSD inM.2-SSDand the LTE/5G modem inCELLULAR LTE/5G. - Connect the PCIe FFC cable to the Expansion Board. Insert the
end labelled
Edge AIinto the PCIe FFC connector on the Expansion Board. Align the Pin 1 arrow on the cable with the corresponding marking on the connector, fully insert, and close the latch. - Stack the Raspberry Pi 5 on top. Lower the Raspberry Pi 5 onto the 4× 5 mm male-female spacers. The Raspberry Pi 5's mounting holes should line up over the spacers, and the pogo pins on the Expansion Board's top side should make contact with the underside of the Raspberry Pi 5 GPIO header (two 5V pads and two GND pads).
- Secure the stack. Hand-tighten 4× M2.5 Philips screws through the Raspberry Pi 5 mounting holes into the 5 mm spacers. Hand-tighten the remaining 2× M2.5 screws into the Expansion Board's own top-side mounting holes that thread into the 15 mm bottom standoffs.
- Connect the PCIe FFC cable to the Raspberry Pi 5. Insert the end
labelled
Raspberry Pi 5into the Raspberry Pi 5's PCIe connector. Align the Pin 1 arrow, fully insert, and close the latch. - Seat the USB Bridge daughterboard. The USB Bridge PCBA has two vertical USB 3.0 plugs on its underside. Align both plugs with the Raspberry Pi 5's two USB 3.0 (blue) ports, then press straight down until both plugs are fully seated. The daughterboard's other connector mates with the Expansion Board's USB header underneath, routing the internal USB hub to the Raspberry Pi 5. This is the data path for the NVMe and cellular slots.
Finger-tight is the spec. Loose spacers cause intermittent pogo-pin contact, which shows up as power glitches or reboots under load. Over-torquing strips the threads in the Raspberry Pi 5 PCB and the threads are not field-repairable. No power driver.
The cable has two distinct ends. The end labelled Raspberry Pi 5 goes to
the Raspberry Pi 5's PCIe port; the end labelled Edge AI goes to
the Expansion Board's PCIe port. Match the Pin 1 arrow on each end to the
corresponding marking on the PCB connector. A reversed or partially seated
cable produces no PCIe link, and the DX-M1 will not enumerate on
lspci.
The cable is a 40 × 8.5 mm FFC manufactured by Sixfab and is included in the box. A longer cable or a different pitch is not recommended.
Visual reference
Each photograph below isolates one substep so the orientation and seating cues are unambiguous. The numbered Fig. tags correspond to the assembly order shown above.
Edge AI end to the Expansion Board and the Raspberry Pi 5 end to the Raspberry Pi 5, Pin 1 to Pin 1.
Configure /boot/firmware/config.txt and power on
Three lines need to be in /boot/firmware/config.txt before the
DEEPX runtime is installed: one to enable the Raspberry Pi 5's PCIe lane, one to set it to
Gen 3, and one to lift the USB current limit so the Raspberry Pi 5 doesn't pause at boot when
the Expansion Board is drawing power.
Power on the Raspberry Pi 5 (USB-C PD supply connected to the Expansion Board's
USB-C port; the Expansion Board back-powers the Raspberry Pi 5), wait for it to boot to a
terminal, then add the lines below to the end of /boot/firmware/config.txt.
# 1. Open config.txt in your editor of choice sudo nano /boot/firmware/config.txt # 2. Append these three lines at the end of the file: dtparam=pciex1 dtparam=pciex1_gen=3 usb_max_current_enable=1 # 3. Save (Ctrl+O, Enter) and exit (Ctrl+X), then reboot sudo reboot
What each line does
dtparam=pciex1: enables the Raspberry Pi 5's external PCIe x1 lane that the 40 mm FFC cable routes to the DX-M1.dtparam=pciex1_gen=3: pushes the PCIe link from Gen 2 (the safe default on Raspberry Pi OS) to Gen 3. The DX-M1 supports Gen 3, and measured bandwidth jumps from 400–450 MB/s at Gen 2 to 800–900 MB/s at Gen 3.usb_max_current_enable=1: lifts the Raspberry Pi 5's USB current cap. Without this line, the Raspberry Pi 5 pauses at boot and prompts the user to press the on-board button to acknowledge that more than 1.6 A of USB current is being requested.
A power supply under 27 W triggers reduced system performance and an on-screen under-voltage warning. Symptoms include SSD disconnects and random reboots. The official Raspberry Pi 27 W USB-C PSU is the documented minimum; for a full-stack configuration with AI + NVMe + LTE/5G, a 45 W supply is strongly recommended.
The Sixfab APT package installs the kernel driver and runtime, but it does
not edit config.txt on the user's behalf. Adding these lines
before the install means the next reboot brings PCIe Gen 3 up cleanly and the
DX-M1 enumerates at full speed on first boot.
Install the driver and DEEPX runtime
The sixfab-dx APT package installs the kernel driver (via DKMS),
the DEEPX runtime (dxrt-runtime), and the CLI tools
(dxrt-cli, dxtop, run_hello_world). It also
pulls in raspberrypi-kernel-headers automatically so the DKMS build
succeeds. One command does the whole thing.
# Refresh the package index and install the runtime in one go sudo apt update && sudo apt install sixfab-dx
When the installer prompts Do you want to continue? [Y/n], type
Y and press Enter. The driver compiles against your running
kernel via DKMS, so the first install can take 5–10 minutes depending on
connection speed and CPU.
The package downloads the runtime and pulls kernel headers from the Pi OS repositories. After install, the board can run fully offline; AI inference does not need an internet connection.
Because the driver is built through DKMS, it normally rebuilds automatically
when the kernel changes. If after a major OS update the NPU stops appearing,
run lsmod | grep -i dx. If nothing matching dx_dma
is loaded, reinstall the package with sudo apt install --reinstall
sixfab-dx to rebuild the module against the new kernel.
Verify the NPU, NVMe, and cellular subsystems
One command per subsystem confirms the hardware path is up. The NPU check is always required; the NVMe and cellular checks only apply if you installed those M.2 modules.
dxrt-cli -s
Prints the runtime version, kernel-side drivers, on-NPU firmware, PCIe link speed, and per-core voltage, clock, and temperature. Healthy: all three NPU cores at 750 mV, 1000 MHz, temperature 40–55 °C at idle.
Alwayslsblk
The SSD shows up as a USB Mass Storage device, typically /dev/sda (USB-to-NVMe bridge). Healthy: the expected SSD capacity appears under the sda entry.
ping -I usb0 1.1.1.1
A reply confirms the modem is registered and data is flowing. Healthy: ping replies received. Discover your modem's actual interface name with ifconfig first; it varies by device.
Full NPU status with dxrt-cli -s
Run this even if you only installed the DX-M1. It is the single canonical command for confirming the DEEPX runtime, the kernel driver, and the on-NPU firmware are talking to each other.
The DEEPX runtime, the kernel driver (RT Driver and PCIe Driver), and the
on-NPU firmware all carry independent version numbers. A drift between any two
shows up later as silent CPU fallback, version-mismatch errors when loading
.dxnn files, or unstable inference. Catching it here is much
cheaper than catching it after deployment.
# Full hardware and firmware status report dxrt-cli -s
DXRT v3.3.0 ======================================================= * Device 0: M1, Accelerator type --------------------- Version --------------------- * RT Driver version : v2.4.0 * PCIe Driver version : v2.2.0 ------------------------------------------------------- * FW version : v2.5.6 --------------------- Device Info --------------------- * Memory : LPDDR5 5600 Mbps, 3.92GiB * Board : M.2, Rev 1.0 * Chip Offset : 0 * PCIe : Gen3 X1 [01:00:00] NPU 0: voltage 750 mV, clock 1000 MHz, temperature 45'C NPU 1: voltage 750 mV, clock 1000 MHz, temperature 45'C NPU 2: voltage 750 mV, clock 1000 MHz, temperature 45'C =======================================================
Also confirm the PCIe enumeration and kernel-log evidence
# 1. The DX-M1 should enumerate on the PCIe bus lspci # 2. The kernel module dx_dma should have loaded at boot dmesg | grep -i dx
# lspci 00:00.0 PCI bridge: Broadcom Inc. BCM2712 x1 PCI Express Bridge (rev 21) 01:00.0 Processing accelerators: DEEPX Co., Ltd. DX-M1 AI Accelerator (rev 01) # dmesg | grep -i dx [ 2.102285] dx_dma: loading out-of-tree module taints kernel. [ 2.112716] dx_dma_pcie 0001:01:00.0: enabling device (0100 -> 0102) [ 2.112830] dx_dma_pcie 0001:01:00.0: dw->dx_ver: 3 [ 2.182700] dx_dma_pcie 0001:01:00.0: [dx_dma_pcie_probe] Probe Done!! [ 2.799076] dxrt_driver_cdev_init: 1 devices
NVMe SSD (only if installed)
The NVMe slot is connected through the on-board USB 3.2 Gen 1 hub and a Realtek
RTL9210B-CG USB-to-NVMe bridge chip. The operating system sees a USB Mass Storage
device, not a native NVMe block device, so lsblk is the right tool
rather than nvme list.
# 1. Block-device tree; SSD shows as /dev/sda lsblk # 2. USB-side view; RTL9210 NVMe Bridge should be listed lsusb
# lsblk (example with a 256 GB SSD) NAME MAJ:MIN RM SIZE RO TYPE MOUNTPOINTS sda 8:0 0 238.5G 0 disk mmcblk0 179:0 0 29.7G 0 disk ├─mmcblk0p1 179:1 0 512M 0 part /boot/firmware └─mmcblk0p2 179:2 0 29.2G 0 part / # lsusb Bus 002 Device 002: ID 0bda:9210 Realtek Semiconductor Corp. RTL9210 NVMe Bridge Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Sequential read peaks at 380–440 MB/s, write at 350–410 MB/s.
These ceilings come from the 5 Gbps USB bus and 8b/10b encoding overhead, not
the SSD itself. The full setup procedure for the NVMe slot (GPT partition →
ext4 → UUID-based /etc/fstab) lives on the
NVMe Storage
page.
Cellular modem (only if installed)
The cellular slot is also USB-attached, routed through the same internal USB 3.2
Gen 1 hub via the USB Bridge PCBA. The modem enumerates as a USB device in
lsusb, exposes one or more /dev/ttyUSBx serial nodes,
and provides a network interface that's commonly named usb0 but can
vary by modem module.
# 1. Confirm the modem enumerates on the USB hub lsusb # 2. List network interfaces and find the modem's interface name ifconfig # 3. Send a ping out the modem's interface (replace usb0 if needed) ping -I usb0 1.1.1.1
# lsusb (example with a Quectel RM520N-GL) Bus 002 Device 003: ID 2c7c:0125 Quectel Wireless Solutions Co., Ltd. RM520N-GL Bus 002 Device 002: ID 0bda:9210 Realtek Semiconductor Corp. RTL9210 NVMe Bridge Bus 002 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub # ping -I usb0 1.1.1.1 PING 1.1.1.1 (1.1.1.1) from 10.x.x.x usb0: 56(84) bytes of data. 64 bytes from 1.1.1.1: icmp_seq=1 ttl=58 time=42.3 ms 64 bytes from 1.1.1.1: icmp_seq=2 ttl=58 time=38.1 ms
The cellular interface name is device-dependent. Run ifconfig
first to find the actual name on your system; usb0 is the most
common but not guaranteed. Full data-connection setup, APN configuration, AT
commands, and signal-quality monitoring live on the
Cellular Connectivity
page.
lspci, lsblk, or lsusb comes up empty
The most common causes, in order: (1) the 40 mm PCIe FFC is reversed or not fully latched; (2) the M.2 module is not fully seated; (3) the spacers are loose so the pogo pins are not making contact; (4) the USB-C bridge between the Expansion Board and the Raspberry Pi 5 is loose. Power off, reseat, and try again. See Troubleshooting for the full per-symptom diagnostic flow.
Run your first inference on the NPU
The sixfab-dx package ships with a pre-compiled YOLOv8 detection
demo wired up to run_hello_world. A single command launches it on the
DEEPX NPU and opens a window with bounding boxes drawn in real time.
run_hello_world
A window opens showing the live feed (camera or stored video) with bounding boxes drawn around detected objects in real time.
A live detection window means YOLOv8 is executing on the DEEPX NPU, not on the Raspberry Pi CPU. That's the Edge AI Expansion Board doing its job, with zero load on the Raspberry Pi 5's ARM cores. Concurrent NVMe writes and LTE/5G traffic do not measurably degrade this throughput.
Watch the NPU work in real time
Open a second terminal while the demo is running and launch dxtop.
It prints per-core utilisation, voltage, clock, and temperature, much like
htop for the NPU.
dxtop
Press q to quit. The DX-M1 begins thermally throttling at
approximately 90 °C; sustained inference well below that is the goal, and
dxtop is how you watch for it. The full set of monitoring tools and
how to plug them into production fleets is documented separately in
System Monitoring.
All AI inference happens on-device. There is no outbound data flow unless
you build one into your application. If you also installed the NVMe SSD,
run_hello_world does not write to it by default; logging inference
results to the NVMe is something your application configures explicitly.
Where to next
YOLOv8 is now running on the DEEPX NPU. The hardware, OS, and runtime stack are healthy, and the next chapter is AI Model Deployment: choose more pre-compiled models, bring your own trained model to the NPU, or instrument the deployment for production.
dxrt-cli and dxtop. Read NPU telemetry, surface
it to dashboards, and watch deployments in real time.
Monitor the NPU →
Updated about 2 hours ago