Overview

The Sixfab AI HAT+ for Raspberry Pi 5 is a PCIe edge AI accelerator with a DEEPX NPU, delivering up to 13 or 25 TOPS of real-time inference. Explore its architecture, capabilities, and professional use cases for edge AI workloads.

Sixfab AI HAT+ for Raspberry Pi 5

A HAT+ specification compliant accelerator for Raspberry Pi 5, carrying a DEEPX DX-M1M (25 TOPS at INT8) or DX-M1ML (13 TOPS at INT8) NPU. Connects over PCIe Gen 3 x1 via a 16-pin FFC cable, and runs vision models on-device. Intelligented by DEEPX. Built on Raspberry Pi.

25 TOPS · DX-M1M 13 TOPS · DX-M1ML Raspberry Pi 5 PCIe Gen 3 x1 HAT+ compliant
Sixfab AI HAT+ mounted on Raspberry Pi 5 with 16-pin FFC cable connecting the PCIe port, top-down product photograph
AI HAT+ · Overview · Intelligented by DEEPX · Built on Raspberry Pi
What is the Sixfab AI HAT+?

The Sixfab AI HAT+ for Raspberry Pi 5 is a HAT+ specification compliant accelerator carrying a DEEPX DX-M1M (25 TOPS at INT8) or DX-M1ML (13 TOPS at INT8) NPU. It connects to the Raspberry Pi 5 over PCIe Gen 3 x1 through a 16-pin FFC cable, runs compiled vision models on-device, and draws power through the standard 40-pin GPIO header. Intelligented by DEEPX. Built on Raspberry Pi.

NPU
25 TOPS
INT8 · DX-M1M variant
Host link
PCIe Gen 3
x1 · 16-pin FFC cable
Typical power
4.8 W
DX-M1M sustained · 3.5 W on DX-M1ML
Form factor
HAT+
65 × 56.5 mm

What the AI HAT+ is

The Sixfab AI HAT+ is an add-on board for Raspberry Pi 5 that adds a dedicated DEEPX neural processing unit to the system. Vision models compiled to the DXNN format run on the NPU; the Raspberry Pi 5 keeps handling I/O, networking, application logic, and any pre/post-processing that is not offloaded.

The board is mechanically and electrically compliant with the official Raspberry Pi HAT+ specification. It draws all of its power from the Raspberry Pi 5's 40-pin GPIO header (5 V DC, 3 A rated input), with no external power connector, and identifies itself to the Raspberry Pi 5 via an onboard EEPROM on the HAT+ ID bus. PCIe data does not run through the GPIO header: it is routed over a 16-pin FFC cable from the Raspberry Pi 5's external PCIe port to the connector on the HAT+.

Inference runs entirely on-device. After installation, no internet connection is required at runtime. The board is shipped today with a vision focus: object detection, classification, segmentation, and similar tasks. LLMs are on the DEEPX silicon roadmap and Sixfab will support them as the silicon enables. No dates.

Two variants

The AI HAT+ ships in two variants. They share the same PCB design, the same HAT+ form factor, the same connectors, and the same software stack. The NPU on board is what changes.

Sixfab AI HAT+ (DX-M1M)
DEEPX DX-M1M · 25 TOPS
Top variant
Compute 25 TOPS at INT8
NPU memory 1 GB LPDDR4x
Host interface PCIe Gen 3 x1
Typical power 4.8 W
Recommended where the full 25 TOPS at INT8 is the design constraint: multi-stream 1080p, higher-resolution single-stream, larger compiled models, or production deployments with margin for future model growth.
Sixfab AI HAT+ (DX-M1ML)
DEEPX DX-M1ML · 13 TOPS
Lite variant
Compute 13 TOPS at INT8
NPU memory 512 MB LPDDR4x
Host interface PCIe Gen 3 x1
Typical power 3.5 W
The cost-efficient entry point for single-stream vision applications, prototypes, and budget-sensitive deployments where 13 TOPS at INT8 is sufficient headroom for the workload.
Buying for CM5? You need a different PCIe cable

The 16-pin FFC cable shipped in the AI HAT+ box does not fit the Raspberry Pi CM5 IO Board's PCIe connector. If you are deploying on the CM5 + Raspberry Pi CM5 IO Board path, plan to source a CM5-compatible PCIe cable separately before assembly. The Raspberry Pi 5 (primary) path uses the bundled cable as-is.

Quantization and accuracy

The DEEPX silicon runs INT8 only. The DXNN compiler quantizes models from FP32 to INT8 automatically; expect approximately 2 % accuracy loss compared with the original trained model. Plan benchmarks and acceptance criteria around the quantized model, not the FP32 baseline.

Key features

DEEPX NPU on board
Either DX-M1M (25 TOPS) or DX-M1ML (13 TOPS) at INT8 precision, soldered to the PCB. Multi-model execution is supported via RunAsync in the dxrt runtime API.
PCIe Gen 3 x1, no GPIO consumed
Data link runs over a 16-pin FFC cable from the Raspberry Pi 5's external PCIe port. The 40-pin header is used only for power, ground, and the HAT+ ID EEPROM. Every other GPIO stays free for stacked HATs and user peripherals.
HAT+ specification compliant
Full mechanical and electrical compliance with the Raspberry Pi HAT+ specification. The onboard EEPROM, with 3.9 kΩ pull-ups on the ID bus, allows the Raspberry Pi 5 to auto-load the device tree fragment for the DEEPX NPU.
Two software paths
Start with the Sixfab Model Zoo for pre-compiled DXNN models, or use the DXNN SDK for the full ONNX → DXNN compile flow. The Sixfab × Ultralytics acceleration path takes a labeled dataset to a deployed custom model in days.
On-device inference, no cloud
After the runtime install, the system runs fully offline. No frames or model outputs leave the Raspberry Pi 5 unless the user application explicitly forwards them, making it a fit for privacy-sensitive vision deployments.
Power profile sized to embedded
Typical sustained NPU draw is 4.8 W (DX-M1M) or 3.5 W (DX-M1ML). System power for Raspberry Pi 5 + AI HAT+ stays well below the 27 W envelope of the official Raspberry Pi USB-C PD supply, which is the standard PSU for this configuration.

How inference flows through the system

The pipeline keeps the Raspberry Pi 5 in charge of capture and pre-processing, hands the prepared input to the DEEPX NPU over PCIe, and returns raw outputs to the application for post-processing and routing.

Inference pipeline
Step 1
Capture
CSI, USB, or IP camera feeds frames into the Raspberry Pi 5. The Raspberry Pi handles capture, not the HAT+.
Step 2
Pre-process on Raspberry Pi 5
CPU-side resize, color-space, and tensor packing. Image format is fixed by the model's input definition.
Step 3
NPU inference
DEEPX NPU runs the compiled DXNN model. INT8 execution. Tensors travel over PCIe Gen 3 x1.
Step 4
Post-process & act
User code parses outputs, runs filters such as NMS, and routes results to display, logs, or RTSP.
Why PCIe
PCIe Gen 3 x1 gives the NPU a dedicated, deterministic data path separate from USB and the GPIO header. Pre-processing on the Raspberry Pi 5 CPU is typically the first bottleneck before the NPU saturates: a Raspberry Pi 5 with 8 GB RAM and a DX-M1M variant can sustain up to four 1080p streams through this pipeline before CPU work bounds throughput.

Software: two paths to a running model

Both paths run on top of the same DEEPX runtime (dxrt-runtime) and the kernel driver shipped from the Sixfab APT repository. The difference is what is on disk before dxrt-cli -s is run.

Recommended starting path

Validate the hardware first with the Sixfab Model Zoo: a Raspberry Pi 5, an AI HAT+, and a YOLOv8n DXNN file are enough to confirm the NPU is detected and producing correct output. From there, move to the DXNN SDK when the application needs a model that is not in the zoo or a custom-trained one.

What you can build

The AI HAT+ is sized for embedded vision workloads where local inference, deterministic latency, and a fixed power envelope matter. Examples below; this is a sample, not a limit.

AI cameras & on-prem security
Object detection, intrusion alerts, anomaly classification. Frames stay on the device, only events leave it.
Smart-city & infrastructure
Traffic and pedestrian analytics at the intersection, parking-lot occupancy, transit hub counting, all without streaming raw video.
Robotics perception
AMRs, robot arms, and warehouse robots that need fast, deterministic visual perception inside their own compute envelope.
Drones & autonomous platforms
Lightweight CV for obstacle detection, landing-zone classification, and visual tracking where a sub-5 W inference budget matters.
Industrial inspection
Defect detection on assembly lines, quality control of products, predictive maintenance from machine-vision feeds.
Edge inference nodes
Raspberry Pi 5 + AI HAT+ as a compact, repeatable inference unit, easy to scale at the network level rather than per-board.

What the AI HAT+ does not do

Stating limits up front is part of the brand contract. Plan deployments against the lines below; do not plan against marketing speculation.

Vision today, LLMs later
The DEEPX silicon is sized for vision workloads. LLM support is on the DEEPX roadmap and Sixfab will support it as the silicon enables. No dates.
No on-device training
Train on a host machine, export to ONNX, then compile with the DXNN compiler — or use the Sixfab × Ultralytics acceleration path.
Not hot-pluggable
The Raspberry Pi 5 must be powered off and the USB-C cable disconnected before mounting or removing the AI HAT+.
INT8 only on the NPU
The DXNN compiler quantizes FP32 to INT8 automatically. Expect approximately 2 % accuracy loss versus the original trained model.
Needs the 27 W PSU
Standard 5 V / 3 A (15 W) supplies are insufficient. The Raspberry Pi 27 W USB-C PD power supply is required to avoid under-voltage warnings and throttling.

Compatibility

The statement below is canonical and is reused on the Getting Started, Quickstart, and FAQ pages.

Supported host platforms: Raspberry Pi 5, and Raspberry Pi Compute Module 5 via the official Raspberry Pi CM5 IO Board. Not supported: Pi 4, CM4, non-Raspberry Pi SBCs.

Supported host platforms
Supported
  • Raspberry Pi 5, the primary host platform.
  • Raspberry Pi Compute Module 5 via the official Raspberry Pi CM5 IO Board.
Not supported
  • Raspberry Pi 4 and earlier.
  • Compute Module 4 and earlier.
  • Non-Raspberry Pi SBCs (Orange Pi, Rock Pi, Jetson, etc.).
CM5 + IO Board path: the 16-pin FFC cable shipped with the AI HAT+ does not fit the IO Board's PCIe connector. A different cable is required. See the FAQ for the cable detail.

Recommended bring-up kit

Everything needed to get a Raspberry Pi 5 and an AI HAT+ from the box to a running inference. The left column is what the AI HAT+ ships with; the right column is what to buy alongside it.

In the box
6 items
  • 01
    AI HAT+ board
    The accelerator itself, with the DEEPX DX-M1M or DX-M1ML NPU soldered on. HAT+ form factor, 65 × 56.5 mm.
  • 02
    PCIe FFC cable
    16-pin, EMI-shielded. Connects the Raspberry Pi 5's external PCIe port to the AI HAT+. Marked RPi5 on one end and HAT on the other.
  • 03
    16 mm stacking header
    2 × 20 female, 2.54 mm pitch. 8.5 mm plastic body, 12.3 mm pin length. Replaces the Raspberry Pi 5's stock header when an active cooler sits underneath.
  • 04
    M2.5 spacers
    16 mm, female–female. Four pieces. Set the clearance between the Raspberry Pi 5 PCB and the AI HAT+.
  • 05
    M2.5 × 5 mm plastic screws
    Four pieces. Secure the AI HAT+ to the spacers. Finger-tight only; over-torquing strips the Raspberry Pi 5 PCB threads.
  • 06
    Passive cooler
    20 × 20 mm, black anodised aluminium. Sits on the DEEPX NPU. Sufficient for typical workloads; add a 3.3 V micro fan via the on-board JST for sustained 100 % NPU load.
You'll also need
Buy separately
  • 01
    Raspberry Pi 5
    4 GB or 8 GB. The 8 GB variant is recommended for multi-stream or heavy pre-processing workloads.
  • 02
    Raspberry Pi 27 W USB-C PD power supply
    The official 27 W supply. Standard 5 V / 3 A (15 W) chargers are not enough and trigger under-voltage warnings when the NPU starts inferring.
  • 03
    microSD card
    Class 10 / A2, 32 GB or larger. Holds Raspberry Pi OS, dxrt-runtime, and any compiled DXNN model files.
  • 04
    Camera Optional
    A Raspberry Pi Camera Module, a USB camera, or an IP camera (RTSP). Only needed for live-video pipelines; recorded video files work without one.
Partnership lockups
Intelligented by DEEPX. Built on Raspberry Pi.

DEEPX silicon. Raspberry Pi host. Sixfab integration, software stack, and support.