Pinout & GPIO
Ensure precise hardware integration with the complete AI HAT+ pinout and GPIO mapping for Raspberry Pi 5, covering interface definitions, GPIO passthrough, and PCIe connectivity.
Pinout & GPIO
Pin-by-pin map of how the Sixfab AI HAT+ for Raspberry Pi 5 connects to the host: the 40-pin GPIO header consumption, the 16-pin FFC PCIe link, the HAT+ EEPROM bus, and the electrical limits that apply to every signal on the board. Intelligented by DEEPX. Built on Raspberry Pi.
The Sixfab AI HAT+ uses only 6 pins on the Raspberry Pi 5 GPIO header: 5 V power (pins 2 and 4), 3.3 V logic (pins 1 and 17), and the HAT+ EEPROM bus on BCM 0 / BCM 1 (pins 27 and 28), plus shared ground. The high-speed PCIe Gen 3 x1 link to the NPU runs over a separate 16-pin FFC cable, so every GPIO, SPI, I²C, UART, and PWM pin on the header stays free for your application or a stacked HAT.
40-pin GPIO header
AI HAT+ consumes only power and HAT+ EEPROM pins on the Raspberry Pi 5 GPIO header. Every GPIO, SPI, I²C (other than the ID bus), UART, and PWM pin remains free for your application or stacked HATs.
Electrical characteristics
Voltage levels, supply limits, and protection that apply across the AI HAT+ interface to the Raspberry Pi 5.
Pin assignment by function
Pins grouped by what they do on the AI HAT+ interface: power rails, the HAT+ EEPROM bus, and the 28 GPIO that pass through unused.
Power rails
HAT+ EEPROM (I²C ID bus)
Pins 27 and 28 (BCM 0 / BCM 1) are reserved by the Raspberry Pi HAT+ specification as the EEPROM identification bus on every HAT+ board, including AI HAT+. Do not connect user peripherals to these pins while AI HAT+ (or any other HAT+ device) is mounted.
Free GPIO available to the user
Every pin not listed above passes through unused. AI HAT+ does not break out or consume any UART, SPI, PWM, or I²C 1 line; the 28 pins below remain fully available for your peripherals or stacked HATs.
BCM GPIO quick reference
Summary of which Broadcom (BCM) GPIO numbers AI HAT+ touches, and which it doesn't.
HAT stacking
AI HAT+ can be physically stacked with other HATs. Because it consumes almost no GPIO, conflicts are rare, but you need the right hardware and should check EEPROM addressing.
Stacking requirements
- Extra-long pass-through stacking headers required. AI HAT+ ships with standard headers. To stack another HAT on top, replace the headers with extra-long pass-through headers, or use a header extender between the two boards. Not included in the box.
- Minimum header height: clearance above the NPU. The stacking headers must lift the upper HAT clear of every tall component on AI HAT+. The dominant constraint is the DEEPX NPU package and its thermal pad, which together set a board Z-height of 6.56 mm above the AI HAT+ PCB (no heatsink). After accounting for the 40-pin header mate depth on the upper HAT, the practical minimum stacking-header height is therefore in the range of standard 14–17 mm pass-through headers commonly used for Pi HATs.
- Check HAT+ EEPROM coexistence. BCM 0 and BCM 1 are the HAT+ ID bus. If the stacked HAT also has an EEPROM on this bus, verify the device tree fragments do not conflict. The AI HAT+ EEPROM is configured for stackable coexistence on the ID bus.
- Keep the PCIe FFC routed clear. The 16-pin FFC cable runs between AI HAT+ and the Raspberry Pi 5 regardless of what is stacked above. Route it so it is not pinched by the upper HAT.