Pinout & GPIO
Ensure precise hardware integration with the complete AI HAT pinout and GPIO mapping for Raspberry Pi 5, covering interface definitions, GPIO passthrough, and PCIe connectivity for reliable signal routing.
Pinout & GPIO
Pin-by-pin map of how the Sixfab AI HAT+ for Raspberry Pi 5 connects to the host: the 40-pin GPIO header consumption, the 16-pin FFC PCIe link, the HAT+ EEPROM bus, and the electrical limits that apply to every signal on the board. Intelligented by DEEPX. Built on Raspberry Pi.
The Sixfab AI HAT+ consumes only 12 of the 40 pins on the Raspberry Pi 5 GPIO header: 5 V power (pins 2 and 4), 3.3 V logic (pins 1 and 17), eight ground returns, and the HAT+ EEPROM bus on BCM 0 / BCM 1 (pins 27 and 28). The high-speed PCIe Gen 3 x1 link to the NPU runs over a separate 16-pin FFC cable, so every GPIO, SPI, I²C, UART, and PWM pin on the header stays free for your application or a stacked HAT.
40-pin GPIO header
AI HAT+ consumes only power and HAT+ EEPROM pins on the Raspberry Pi 5 GPIO header. Every GPIO, SPI, I²C (other than the ID bus), UART, and PWM pin remains free for your application or stacked HATs.
Electrical characteristics
Voltage levels, supply limits, and protection that apply across the AI HAT+ interface to the Raspberry Pi 5.
3.9 kΩPin assignment by function
Pins grouped by what they do on the AI HAT+ interface: power rails, the HAT+ EEPROM bus, ground, and the 28 GPIO that pass through unused.
Power rails
HAT+ EEPROM (I²C ID bus)
Pins 27 and 28 (BCM 0 / BCM 1) are reserved by the Raspberry Pi HAT+ specification as the EEPROM identification bus on every HAT+ board, including AI HAT+. Do not connect user peripherals to these pins while AI HAT+ (or any other HAT+ device) is mounted.
Ground
Free GPIO available to the user
Every pin not listed above passes through unused. AI HAT+ does not break out or consume any UART, SPI, PWM, or I²C 1 line; the 28 pins below remain fully available for your peripherals or stacked HATs.
BCM GPIO quick reference
Summary of which Broadcom (BCM) GPIO numbers AI HAT+ touches, and which it doesn't.
PCIe FFC connector
AI HAT+ communicates with the Raspberry Pi 5 through a dedicated 16-pin FFC (Flexible Flat Cable) connector, separate from the 40-pin GPIO header. This cable carries the high-speed PCIe Gen 3 x1 data link to the NPU.
Signal classes on the cable
The 16 conductors split into four functional groups. Differential pairs carry the high-speed data and the reference clock; control lines manage link bring-up and power; ground returns sit between every signal group for return-current integrity.
Pin-by-pin assignment
HAT_PWR_OFF pin on the 40-pin header.The 16-pin FFC cable has two clearly labeled ends. Connect the end marked Raspberry Pi 5 to the Raspberry Pi 5's PCIe FFC port, and the end marked HAT to the AI HAT+ connector. Inserting the cable backwards prevents NPU detection on lspci and may damage the connector latch.
Always power off the Pi 5 before connecting or disconnecting the cable. AI HAT+ does not support hot-plug. The full mount, cable, and power-on sequence is documented in the Quickstart.
Fan connector
A dedicated 2-pin JST connector on AI HAT+ accepts a 3.3 V micro fan for active NPU cooling. The fan is optional and not included in the box.
The 2-pin JST connector on AI HAT+ is not reverse-polarity protected. Connecting a fan with the wires swapped will reverse-bias the motor and can permanently damage it, the fan controller, or both. Before plugging in any fan, confirm:
- Pin 1 = 3.3 V (positive supply, red wire on most micro fans).
- Pin 2 = GND (ground return, black wire on most micro fans).
Pin 1 is the pin nearest the silkscreen + marker on the AI HAT+ PCB. If your fan came with a non-keyed connector, check the wire colors against the manufacturer's datasheet before applying power.
+ on the AI HAT+ silkscreen.Passive cooling via the included thermal pad is sufficient for typical workloads. For deployments running sustained 100 % NPU utilization, especially in enclosed or warm environments, connect a 3.3 V micro fan via this header. Thermal limits and recommended cooling are documented in Hardware Reference.
HAT stacking
AI HAT+ can be physically stacked with other HATs. Because it consumes almost no GPIO, conflicts are rare, but you need the right hardware and should check EEPROM addressing.
Stacking requirements
- Extra-long pass-through stacking headers required. AI HAT+ ships with standard headers. To stack another HAT on top, replace the headers with extra-long pass-through headers, or use a header extender between the two boards. Not included in the box.
- Minimum header height — clearance above the NPU. The stacking headers must lift the upper HAT clear of every tall component on AI HAT+. The dominant constraint is the DEEPX NPU package and its thermal pad, which together set a board Z-height of 6.56 mm above the AI HAT+ PCB (no heatsink). After accounting for the 40-pin header mate depth on the upper HAT, the practical minimum stacking-header height is therefore in the range of standard 14–17 mm pass-through headers commonly used for Pi HATs.
- Check HAT+ EEPROM coexistence. BCM 0 and BCM 1 are the HAT+ ID bus. If the stacked HAT also has an EEPROM on this bus, verify the device tree fragments do not conflict. The AI HAT+ EEPROM is configured for stackable coexistence on the ID bus.
- Keep the PCIe FFC routed clear. The 16-pin FFC cable runs between AI HAT+ and the Raspberry Pi 5 regardless of what is stacked above. Route it so it is not pinched by the upper HAT.
Stacking compatibility
Updated 5 days ago